The present invention relates generally to shift registers and more specifically to variable length shift registers.
Shift registers are serial devices wherein data is inputted in the first stage and is progressively transferred down the length of the shift register to the last stage. Prior art shift registers have been built out of a plurality of flip flops wherein the data is provided at the data input D of the flip flop is connected to the data output Q of the previous flip flop.
Techniques in the prior art to vary the length of the shift register have included selectively changing the input port in the cascaded connected flip flops or in the alternative selectively changing the output port. As illustrated in FIG. 1, each of the stages 1 through N through N+M has input logic whose output is connected to the terminal D of the flip flop and whose input combines the data input terminal, the Q output of the previous stage and a select signal for that stage. One of the select signals activates its logic to select which stage will become the input terminal of the shift register with the N+M stage always being the output stage. If stage 1 is activated as the input terminal, the shift register has N+M stages. If the N stage is selected as the input terminal then the shift register has M+1 stages.
As an alternative, the prior art of FIG. 2 has the input connected to the first stage 1 and the output Q of each of the flip flops connected through a switch or logic gate to the data output. Selector control signal at the logic gate selects one of the output stages output Q to provide the output data signal and thereby vary the length of the shift register. If the N output logic gate is selected, the shift register has a length of N stages. If the N+M output logic gate is selected, the shift register has a length of N+M.
Each of the shift registers of FIGS. 1 and 2 require decoding logic, normally AND gates to provide the select signals. This increases the overhead.
In use of these prior art systems, the shifting of data between the shift registers each includes a time delay for the transmission. Similarly a flip flop has an input and output stage and therefore includes a substantial number of transistors. Also since the data is shifting, all stages are active or powered during each cycle.
In the shift register of FIGS. 1 and 2, two cycles are required. The first cycle clocks data into the flip flop and the second cycle clocks it out. This adds an additional delay to the transmission of the information through the shift register.
Thus it is an object of the present invention to provide a shift register of reduced size.
Another object of the present invention is to provide a shift register with reduced time delay.
Yet still another object of the present invention is to provide a variable length shift register with a minimum number of transistors and time delay.
A still even further object of the present invention is to provide a variable length shift register of reduced area.
An even further object is to provide a shift register having reduced power consumption.
These and other objects of the invention are attained by forming the shift register as a plurality of memory locations in a memory array where the input port for writing into the memory and the output port for reading out of the memory are sequenced along the array. Thus the input and output ports are shifted with respect to the array instead of the information shifting with respect to fixed input and output ports and only the input and the output cell are active or consuming power at each cycle. The length or number stages of the shift register may be varied by changing the displacement or offset of the output or reading port to the input or writing port in the sequence. By using dual port memories, the reading cycle and writing cycle may be performed simultaneously.
Where the number of desired stages is less than the size of the memory, the sequencing may continue across the length of the memory and then the reading and writing may be restarted respectively as they reach the end of the array. Alternatively, restarting may be at the position in the array equal to the length of the desired shift register stages. The sequencing may be performed by a resettable counter or shift register instead of the logic of the prior art, thereby reducing overhead. Using the second method where the restart is at the desired length of the shift register, the stage being written into is adjacent the stage being read. Using a dual port memory cell, a single select line may be used to simultaneously select reading one cell and writing into an adjacent cell. Where a single select line is used for simultaneously reading and writing, a separate storage device or register is provided and it is written into when the first stage is being read from and the register is read from when the last stage is being written into.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.